1. Field of Invention
This invention relates to a timing generator capable of generating a timing signal for an LSI tester and a pulse generator; and more particularly, to a low power consuming timing generator which is capable of setting a delay time with high accuracy and high resolution through use of a digital signal.
2. Description of the Prior Art
Conventionally, there has been used a programmable delay line, which may also be called a timing vernier, for setting with high accuracy a measurement timing for a digital LSI test system.
One example of such delay line makes use of a gate delay or a ramp generator. However, when a gate is used, the structure of the delay line is necessarily large so that it becomes necessary to make uniform the delay differences for switching. This makes it difficult to obtain linearity and monotonicity. Furthermore, when a ramp generator is used, the ramp waveform requires linearity so that a high quality capacitor is necessitated. Moreover, since the repetition frequency is limited by the ramp waveform, a high speed digital to analog converter is needed. This results in the ramp generating becoming unduly complex.
To solve the above problem, an apparatus, using a mirror amplifier based on feedback capacitance, was invented by the inventor hereof and is disclosed in U.S. Pat. No. 5,138,204. However, such an apparatus uses a shortened discharge time to speed operation. In order to shorten the discharge time, a buffer, comprising an emitter follower, may be added to the output of the differential amplification circuit of the mirror amplifier. In that case, the stability of the circuit may he affected since the circuit is or the feedback type. Furthermore, if an attempt is made to lower the output impedance of the mirror amplifier, without using the emitter follower, the load resistance has to be lowered, which results in increase of power consumption.